1. Field of the Invention
The present invention relates to a semiconductor storage device, and more specifically, to a semiconductor storage device and a method of controlling the same which enable stable operation of a sense amplifier.
2. Description of Related Art
Electronic devices such as a computer generally include data storing means storing data. One of the semiconductor storage devices employed as the data storing means includes DRAM (Dynamic Random Access Memory). The DRAM has a relatively simple structure, which enables high integration.
FIG. 10 shows one example of a typical DRAM circuit as a related art. As shown in FIG. 10, a DRAM circuit 1 includes a memory cell 10 and a sense amplifier 20 connected to a bit line pair formed of bit lines DT and DB. A PMOS transistor 25 is connected between the sense amplifier 20 and a power supply voltage terminal 30, and an NMOS transistor 26 is connected between the sense amplifier 20 and a ground terminal 31.
A gate of the PMOS transistor 25 is connected to a signal line 52 transmitting a control signal SAP. A gate of the NMOS transistor 26 is connected to a signal line 53 transmitting a control signal SAN.
The memory cell 10 includes a gate transistor 11 and a capacitor 12 for storing data. The gate transistor 11 is connected between the bit line DT and the capacitor 12, and a word line 51 transmitting a word select signal WL is connected to a gate of the gate transistor 11.
The sense amplifier 20 includes PMOS transistors 21 and 22 and NMOS transistors 23 and 24. The PMOS transistor 21 and the NMOS transistor 23, and the PMOS transistor 22 and the NMOS transistor 24 are connected in series between the nodes A1 and A2, respectively. Further, a drain of the PMOS transistor 21 and a drain of the NMOS transistor 23 are connected to the bit line DT, and a drain of the PMOS transistor 22 and a drain of the NMOS transistor 24 are connected to the bit line DB. A gate of the PMOS transistor 21 and a gate of the NMOS transistor 23 are connected to the bit line DB, and a gate of the PMOS transistor 22 and a gate of the NMOS transistor 24 are connected to the bit line DT.
When the word select signal, WL is raised, the gate transistor 11 is turned on. Accordingly, the bit line DT and the capacitor 12 are electrically connected and the charge is supplied to the bit line DT. Hence, there is caused a small potential difference between the bit lines DT and DB. The sense amplifier 20 which is activated amplifies the potential difference to the power supply voltage and the ground voltage. Then the data stored in the capacitor 12 is read out by the amplified potential difference.
When the sense amplifier 20 is activated, one of the bit lines DT and DB which has a higher potential is raised to the power supply voltage VDD through the PMOS transistors 21 and 22, and the other of the bit lines DT and DB which has a lower potential is lowered to the ground voltage VSS through the NMOS transistors 23 and 24. The operation of raising the potential of the bit line to the power supply voltage VDD is started by turning on the PMOS transistor 25, and the operation of lowering the potential of the bit line to the ground potential VSS is started by turning on the NMOS transistor 26.
Generally, as a timing at which the sense amplifier 20 is activated, the NMOS transistor 26 is turned on earlier than the PMOS transistor 25, and the NMOS transistors 23 and 24 are operated earlier than the PMOS transistors 21 and 22. The operation of operating the NMOS transistor earlier than the PMOS transistor is effective for stabilizing the operation of the sense amplifier 20.
This is because current driving ability and balance of the threshold value voltage of the transistors forming the sense amplifier influence on the important factor for determining the sensitivity of the sense amplifier. For example, regarding the influence of the balance of the threshold value voltage, if the difference of the threshold value voltages of the transistors 21 to 24 forming the sense amplifier 20 is at least 100 mV, then the sensitivity of the sense amplifier decreases by 100 mV. The PMOS transistor generally has a lower current driving ability, higher threshold value voltage Vth, and larger variation of the threshold value voltage Vth than the NMOS transistor. Therefore, it is needed for the stable operation of the sense amplifier 20 to operate the NMOS transistor earlier whose current driving ability is higher, the threshold value voltage Vth is relatively lower, and the variation of the threshold value voltage Vth is smaller.
Now, if the power supply voltage decreases down to around 3.3 V, the current driving ability of the PMOS transistor 25 connected between the sense amplifier 20 and the power supply voltage terminal 30 decreases, and the delay occurs in the amplification operation of the potential difference between the bit lines DT and DB. Therefore, a technique of preventing the delay of the amplification operation of the potential difference between the bit lines DT and DB by the sense amplifier in the power supply voltage of around 3.3 V is disclosed in Japanese Unexamined Patent Application Publication No. 10-269772. FIG. 11 shows a circuit of Japanese Unexamined Patent Application Publication No. 10-269772. FIG. 12 shows a timing chart of this circuit. In Japanese Unexamined Patent Application Publication No. 10-269772, the sense amplifier 20 is overdriven by VPP which is higher than the power supply voltage VDD. The transistor 25 between the high voltage VPP and the sense amplifier is turned on earlier than the transistor 26 between the ground voltage and the sense amplifier. Hence, even when the power supply voltage VDD is around 3.3 V and the current driving ability of the PMOS transistor decreases, the speed of the amplification operation of the potential difference between the bit lines DT and DB is not lowered due to the sense amplifier 20. Although the sense amplifier 20 disclosed in Japanese Unexamined Patent Application Publication No. 10-269772 is overdriven by the high voltage VPP from time t2 to t3, time t3 at which the NMOS transistor starts the operation is earlier than time t4 at which the voltage is raised to the power supply voltage VDD.
Along with the miniaturization and high integration of the recent manufacturing process, the variation of the threshold value voltage of the PMOS transistor is about the same or smaller than the variation of the threshold value voltage of the NMOS transistor depending on the generations of the manufacturing process.
Further, the power supply voltage has been decreasing, which is typically around 3.3 V or lower. For example, the power supply voltage has been decreasing down to about 1.2 V or lower such as a DRAM embedded system LSI. Although the power supply voltage has been decreasing, the threshold value voltage of the transistor has not changed that much. Therefore, the ratio of the threshold value voltage to the power supply voltage has been larger than before.
In order to stably operate the sense amplifier in high speed with low voltage, the factor of the threshold value voltage of the transistor has a greater influence on the operation than the factor of the current driving ability of the above transistor. Accordingly, the variation of the threshold value voltage of the transistor due to the manufacturing process directly influences on the stable high speed operation of the sense amplifier.
Therefore, in order to keep the high speed operation and the stability of the sense amplifier, it is needed to employ the transistor having a smaller variation in the threshold value voltage. Therefore, there is a problem in a technique of operating the NMOS transistor of the sense amplifier earlier than the PMOS transistor as in the related art.